1. Field of the Invention
The present invention relates to a semiconductor device and particularly to an improvement applied in fabricating a semiconductor device with a structure in which a memory circuit, like a dynamic random access memory (DRAM), and a logic circuit are present in the same substrate.
2. Description of Related Art
FIG. 7 is a plan view showing a cell structure of a conventional semiconductor device. In FIG. 7, the reference numeral 1 designates a substrate doped P-type (P conductivity type); 2 designates an N.sup.+ -type diffused region for a drain in one region of the substrate 1; 3 designates an N-type well adjacent to the N.sup.+ -type diffused region 2 in the substrate 1; 4 designates a P.sup.+ -type diffused region for a source located in the N-type well 3; and 5 designates an N.sup.+ -type diffused region for a source located in the N-type well 3, between the P.sup.+ -type diffused region 4 and the N.sup.+ -type diffused region 2.
The reference numeral 6 designates a high potential power line on and separated from the substrate 1 by an insulating layer and connected to the P.sup.+ -type diffused region 4 and the N.sup.+ -type diffused region 5; 7 designates a low potential power line on and separated from the substrate 1 by an insulating layer and connected to the N.sup.+ -type diffused region 2; 8 designates an output signal line connected to the P.sup.+ -type diffused region 4 and N.sup.+ -type diffused region 2; and 9 designates an input signal line on the P.sup.+ -type diffused region 4, located between the high potential power line 6 and the output signal line 8, as well as on the N.sup.+ -type diffused region 2, between the low potential power line 7 and the output signal line 8. The substrate 1 is supplied with a potential V.sub.BB that is lower than the GND potential.
FIG. 8 is a plan view showing a layout of a semiconductor device including a plurality of the cells of FIG. 7. In FIG. 8, each of reference numerals 10 designates a cell as shown in FIG. 1; and each of reference numerals 16 designates a set of signal lines for transferring signals to and from the cells. The cells 10 are arranged in the same direction as indicated by the N-type well 3 disposed at the same side of each cell 10, considering design efficiency, with an auto-router or the like.
Assuming that the high potential power line 6 is connected to a Vcc potential and the low potential power line 7 is connected to the GND (ground). When a signal at the GND level is input through the input signal line 9, the N.sup.+ -type diffused region 2 is controlled to be in a cutoff state, whereas the P.sup.+ -type diffused region 4 is controlled to be in a linear operating state. As a result, a signal at the Vcc level is produced at the output signal line 8.
In contrast, when a signal at the Vcc level is input through the input signal line 9, the P.sup.+ -type diffused region 4 is controlled to be in the cutoff state, whereas the N.sup.+ -type diffused region 2 is controlled to be in a linear operating state. As a result, a signal at the GND level is produced at the output signal line 8.
Thus, the cell operates as an inverter. With such an arrangement, the conventional semiconductor device has a problem called latchup due to a thyristor structure formed in each cell.
FIG. 9A is a cross-sectional view taken along the line 9A--9A of the semiconductor device cell as shown in FIG. 7. In FIG. 9A, the reference symbol Tr1 designates a first bipolar transistor formed between the N-type well 3 and the substrate 1 with the P.sup.+ -type diffused region 4 as its emitter; R1 designates a first resistor composed of the N-type well 3; Tr2 designates a second bipolar transistor formed between the substrate 1 and the N-type well 3 with the N.sup.+ -type diffused region 2 as its emitter; and R2 designates a second resistor including part of the substrate 1. FIG. 9B shows a circuit structure equivalent to the bipolar transistors shown in FIG. 9A.
If a current flows through the first resistor R1 due to some cause, the first bipolar transistor Tr1 will turn on, owing to a voltage across the first resistor R1, which, in turn, brings about a voltage across the second resistor R2 due to the current passing between the emitter and collector of the first bipolar transistor Tr1. As a result, the base-emitter voltage of the second bipolar transistor Tr2 increases, owing to the voltage across the second resistor R2, which increases the current flowing through the first resistor R1. Accordingly, once such an operation has been started with the product of the amplification factor of the first bipolar transistor Tr1 and that of the second bipolar transistor Tr2 exceeding unity, the currents flowing through the bipolar transistors Tr1 and Tr2 continue to increase, leading to substrate breakdown in extreme cases. This operation is called latchup.
To avoid latchup, the semiconductor device shown in FIG. 9A has, in the N-type well 3, the N.sup.+ -type diffused source region 5 between the P.sup.+ -type diffused source region 4 and the N.sup.+ -type diffused drain region 2. This N-type well 3 reduces the resistance of the first resistor R1 including the N-type well 3, which hinders the turning on of the first bipolar transistor Tr1.
Such a structure, however, cannot prevent latchup when the second bipolar transistor Tr2 conducts, owing to fluctuations of its base potential, due to the voltage across the second resistor R2. In particular, latchup can occur frequently in a semiconductor device comprising in the same substrate a logic circuit and a memory circuit, such as a dynamic random access memory (DRAM), because of the fluctuation of the substrate potential V.sub.BB due to the current flowing from the logic circuit to the substrate 1.
To prevent conduction by the second bipolar transistor Tr2 in the semiconductor device as shown in FIG. 9A, it will be possible, instead of reducing the resistance of the second resistor R2, which is very difficult, to widen the space A between the N-type well 3 and the N.sup.+ -type diffused region 2, thereby increasing the base-emitter (VBE) voltage required for the second bipolar transistor Tr2 to turn on. This widening, however, increases the total width W1 of the cell, which hinders fabricating a high density semiconductor device.
In view of this difficulty, it may be possible to take steps against latchup using one of the techniques disclosed in Japanese Published Patent Applications Sho. 61-147564, Hei. 3-239359, Hei. 8-46054, and Hei. 6-97374.
FIG. 10 is a cross-sectional view showing a structure of a conventional semiconductor device including a countermeasure against latchup. In FIG. 10, the reference numeral 13 designates an N-type (N conductivity type) buried diffused region disposed under the N.sup.+ -type diffused region 2; 12 designates an N-type diffused region for isolation, enclosing the N.sup.+ -type diffused region 2, between the surface of the substrate 1 and the N-type buried diffused region 13; and 11 designates a P-type well isolated from the substrate 1 by the N.sup.+ -type diffused region 2 and the N.sup.+ -type diffused region 12. Since the remaining structure is the same as that of the conventional semiconductor device shown in FIG. 7, its description is omitted. The N-type buried diffused region 13 and the N-type diffused region 12 are referred to as an isolation region hereinafter.
The semiconductor device with such a structure can thoroughly solve the latchup problem because the collector of the second bipolar transistor Tr2 is disconnected from the base of the first bipolar transistor Tr1 and the base of the second bipolar transistor Tr2 is disconnected from the collector of the first bipolar transistor Tr1 as shown in FIG. 10. Hence, the thyristor structure shown in FIG. 9B is not present in each cell.
The semiconductor device with such a structure must, however, have the isolation regions 12 and 13 in each cell. These regions result in an increase in the total width W2 of the cell, which hinders high density integration.